1. Field of the Invention
The present invention relates to a semiconductor device with an inductor, in particular to a layout configuration of an inductor.
2. Description of Related Art
In recent years, as the operation of semiconductor devices has become faster, the use of inductors for the purpose of widening the frequency band and/or of matching the impedance has become more common. In external interface buffers, in particular, the improvement in the characteristics by using inductors has become more important.
An example of a configuration of a related semiconductor device with an inductor is explained with reference to FIGS. 15 to 17. FIGS. 15 to 17 show an external output interface buffer as an example. FIG. 15 is a plane view of a layout; FIG. 16 is a cross section along the line XVI-XVI in FIG. 15; and FIG. 17 a circuit diagram corresponding to the layout shown in FIGS. 15 and 16.
In FIG. 17, the circuit includes an inductor 1, an ESD (Electro-Static Discharge) element 2, an output buffer 3, a terminator 4, an external output terminal 5, a first power supply 13, and a connection node 15. The connection node 15 electrically connects the output terminal 5 to the output buffer 3. The inductor 1 is connected between the connection node 15 and the first power supply 13. In this embodiment, the terminator 4 is also connected in series with the inductor 1 between the connection node 15 and the first power supply 13. The ESD element 2 is connected between the connection node 15 and a GND (ground: second power supply). Note that the first power supply 13 supplies a first voltage. Further, the GND, which is the second power supply, supplies a second voltage.
That is, one terminal of the inductor 1 is electrically connected to the terminator 4. The other terminal of the inductor 1 is electrically connected to the ESD element 2, the output buffer 3, and the external output terminal 5. The other terminal of the terminator 4 is electrically connected to the first power supply 13. The other terminal of the ESD element 2 is electrically connected to the GND.
In FIGS. 15 and 16, an inductor 1, an ESD element 2, an output buffer 3, a terminator 4, an external output terminal 5, a second-layer via 6, a second-layer line 7, a first-layer via 8, a first-layer line 9, a contact 10, a wiring layer 11, and a semiconductor substrate 12 are shown. The inductor 1 and the output terminal 5 are formed in the wiring layer 11. The ESD element 2, the output buffer 3, and the terminator 4 are formed in the semiconductor substrate 12. The inductor 1 is formed by a line in the uppermost layer. One terminal of the inductor 1 is connected to the external output terminal 5, which is also formed by a line in the uppermost layer, through the second-layer via 6 and the second-layer line 7. Further, the one terminal of the inductor 1 is also connected to the ESD element 2 and the output buffer 3 through the second-layer via 6, the second-layer line 7, the first-layer via 8, the first-layer line 9, and the contact 10. The other terminal of the inductor 1 is connected to the terminator 4 through the second-layer via 6, the second-layer line 7, the first-layer via 8, the first-layer line 9, and the contact 10.
As disclosed in Japanese Unexamined Patent Application Publication No. 2007-103477, the characteristic of an inductor deteriorates due to the parasitic capacitance generated in its own. Therefore, an inductor is formed so that no wiring layer or element is disposed below the inductor in order to reduce the parasitic capacitance as much as possible. Further, an inductor is often formed so that no element is disposed below the inductor in order to reduce the effect that is exerted on other elements by noise caused by the inductor as well as the effect that is exerted on the inductor by noise caused by other elements as much as possible. That is, an inductor is formed such that no element other than the line used to connect the inductor is disposed below the inductor.